iRazor: a Low Overhead Error Detection and Correction Scheme to Improve Processor Performance

Technology scaling has increased the impact of process variations on the design margins of digital circuits, leading to circuits operating with higher percentages of safety margins. Current technology uses canary circuits, also known as replica circuits, or look up circuits in order to reduce the amount of margin at which the circuit operates, but these approaches still must account for worst case operating conditions and operate conservatively. iRazor is an error detection and correction (EDAC) scheme that allows the circuits to operate at points of first failure or even beyond. iRazor features a flipflop that only adds three additional transistors to a conventional flip-flop and has much lower area and performance overheads than previous EDAC schemes. The iRazor flip flops will be implemented on the critical path of a three stage RISC-V processor using the 32/28 nm 241B process technology. Results will be compared against a RISC-V processor with no EDAC by comparing their energy efficiency and performance.